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Targeting FPGA DSP Slices for a Large Integer Multiplier for Integer Based FHE

机译:针对基于整数的FHE的大型整数乘法器的目标FPGA DSP Slice

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摘要

Homomorphic encryption offers potential for secure cloud computing. However due to the complexity of homomorphic encryption schemes, performance of implemented schemes to date have been unpractical. This work investigates the use of hardware, specifically Field Programmable Gate Array (FPGA) technology, for implementing the building blocks involved in somewhat and fully homomorphic encryption schemes in order to assess the practicality of such schemes. We concentrate on the selection of a suitable multiplication algorithm and hardware architecture for large integer multiplication, one of the main bottlenecks in many homomorphic encryption schemes. We focus on the encryption step of an integer-based fully homomorphic encryption (FHE) scheme. We target the DSP48E1 slices available on Xilinx Virtex 7 FPGAs to ascertain whether the large integer multiplier within the encryption step of a FHE scheme could fit on a single FPGA device. We find that, for toy size parameters for the FHE encryption step, the large integer multiplier fits comfortably within the DSP48E1 slices, greatly improving the practicality of the encryption step compared to a software implementation. As multiplication is an important operation in other FHE schemes, a hardware implementation using this multiplier could also be used to improve performance of these schemes.
机译:同态加密为安全的云计算提供了潜力。但是,由于同态加密方案的复杂性,迄今为止,已实现方案的性能尚不实用。这项工作研究了硬件(特别是现场可编程门阵列(FPGA)技术)的使用,以实现某种程度上和完全同态的加密方案所涉及的构造块,以评估此类方案的实用性。我们专注于为大整数乘法选择合适的乘法算法和硬件体系结构,这是许多同态加密方案的主要瓶颈之一。我们专注于基于整数的完全同态加密(FHE)方案的加密步骤。我们以Xilinx Virtex 7 FPGA上可用的DSP48E1 Slice为目标,以确定FHE方案的加密步骤中的大整数乘法器是否可以适合单个FPGA器件。我们发现,对于FHE加密步骤的玩具大小参数,大整数乘法器可轻松地放入DSP48E1 slice中,与软件实现相比,极大地提高了加密步骤的实用性。由于乘法是其他FHE方案中的重要操作,因此使用此乘法器的硬件实现也可以用于提高这些方案的性能。

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